Lithium-ion battery applications have been integrated into our lives. We can have electric motorcycles, portable power tools and plug-in hybrid vehicles. Whenever electricity is involved, there will be lithium-ion batteries. The fact that lithium-ion battery packs design protection circuits for these batteries has never been more important.
The power FET is a key safety feature in the Battery Management System (BMS) whose primary purpose is to isolate the battery pack from the load or charger under abnormal conditions. This article will discuss how the block is applied and how it is applied to the power FET to ensure safe operation of the Li-Ion battery pack.
The power FET function block does not appear to be complicated: turn on the FET when the charger or load is connected; turn off the FET when an error occurs. To properly function as a power FET, design engineers need to understand load conditions, battery pack limits, and function block circuits.
In battery management systems, power FETs are controlled by cell voltage, battery current, temperature, load, and charge monitor comparisons. Function blocks are built in three ways in the system: (1) through discrete components, which requires additional board space, and the design engineer needs a deep understanding of each sub-block. (2) A power FET IC that integrates most of the sub-function blocks and can be used as a companion IC for a multi-core monitor/equalizer. Power FET ICs are very useful in high cell count applications ("16 cells"), such as solar farms and smart grids. (3) Power FET function blocks in fully integrated BMS ICs such as ISL94202, ISL94203, and ISL94208. The functions of these three schemes are roughly the same. This article explains the intrinsic functions of each sub-block and the design considerations for different applications.
Consider the circuit configuration of Figure 1. The system is a high side series FET configuration connected to the engine. The on state of the power FET depends on the cell voltage of the battery pack, the charge and discharge currents, the temperature, and the state of the monitor pins. Any failure reported by the sub-block will cause one or both FETs to turn off.
Vcell detection, which does not consider cell balancing, is a voltage measurement used to monitor overvoltage, undervoltage, and open cell conditions. Undervoltage conditions are important to detect the no-load condition of the battery pack to prevent the cell from escaping from the acTIve region. The active area of the lithium ion battery is 2.5V - 4.2V. The lithium polymer cell has an active range of 2.5V - 3.6V. Depending on the chemical nature and design, the cell's limiting voltage determines the full load and no-load cell limits. Do not exceed the upper voltage limit when charging the battery, otherwise the battery may be damaged. Most BMS ICs continuously monitor overvoltage and undervoltage conditions regardless of the state of charge of the battery.
After measuring all the cells in the battery pack, it is useful to report the total voltage difference between the strongest cell and the weakest cell. Large battery pack voltage differences can identify open cell or open line events. Most systems have an open line test to ensure that the measurement system is connected to the cells with wires. The open line test is not as frequent as the cell voltage measurement, and the cell voltage difference calculation result can be used as an early warning of system failure.
An open cell event is an internal open circuit or external connection damage. The occurrence of an incident may be slow or sudden. Possible causes of open cell events are aging, poor cell manufacturing quality, or long-term operation in harsh environments. External connection damage is generally caused by poor battery pack construction.
When the battery pack is connected to the load, a large amount of inrush current is generated, and a false alarm of the maximum cell differential pressure may occur. A surge of inrush current due to cell impedance mismatch can result in a severe mismatch in cell voltage. Some chips have a delay in reporting events, while others do not.
Most battery systems used to measure current have three current comparators: discharge short circuit (DSC), discharge overcurrent (DOC), and charge overcurrent (COC). Each comparator generates a delay that allows the current to be greater than the limit for a period of time before taking action.
The load is less controlled than the charger, so fast current discharge detection is required to turn off the power FET to prevent damage to the battery or the power FET itself. When a DSC event occurs, the power FET is often turned off by tens to hundreds of milliseconds. The DSC delay consists of the timing delay and the time required for the power FET to turn off. The power FET is turned off when the gate and source are connected by an isolation resistor. The resistor and gate capacitance form an RC circuit that determines the turn-off time of the FET.
There are many factors to consider when setting the total DSC turn-off time delay. The DSC turn-off time is determined by the time that the battery and circuit are damaged, as opposed to the time that the inrush current is allowed to pass when the load is activated or connected. The DSC turn-off time must be balanced with the turn-off time of the FET. Excessive FET turn-off speed can cause large voltage transients on the cell measurement pins. The pin closest to the power FET is most susceptible to large voltage transients. These transient events are the inductive energy stored in the trace between the power FET and the battery, which is the result of nowhere to divergence when the battery pack suddenly disconnects from the load. The inductor energy diverges to the open load until the voltage rises enough to activate the ESD diode of the connected circuit. If the energy is sufficient, the component will be subjected to excessive electrical stress. The amount of energy stored in the trace is the product of the inductance of the trace and the current flowing to the load. The energy stored in the trace is the most under discharge short-circuit conditions. Filtering at the cell voltage pin helps to reduce the probability of EOS events. In practice, the trace should be as short as possible and as wide as possible. The size and length of the cable between the load and the power FET should also be carefully chosen. This is another factor that can cause high voltage transient events.
Increasing the isolation resistor value between the FET gate and the FET control pin reduces the magnitude of the voltage transient by extending the FET turn-off time. At the same time, this extends the turn-on time of the power FET by the RC time constant involving the FET capacitance. Please note that there are isolation resistors in both cases.
A power FET that is turned off too slowly can cause damage or loss of power FETs. As shown in Figure 2, most power FET product data sheets provide a graph of FET current versus VDS and duration. Consider a 20V battery pack with a short-circuit current of 100A. The figure below shows that the FET can remain running for 1 millisecond under this condition.
In practice, the DSC limit is usually balanced against the inrush current duration. The inrush current can be as large as 100 times or more of the operating current. Figure 3 shows an example of an inrush current transient event where the inrush current peak is 270A and the operating current draw is 8A. If the inrush current is allowed to break through the DSC limit, the FET will switch between the on and off states.
Figure 4 is a battery pack voltage drop caused when the inrush current of Figure 3 flows to the cell. Figure 4 shows the importance of using low-impedance cells and cell-to-cell connections. The inrush current caused the battery pack voltage to drop by 10.8V. The magnitude of the inrush current is reduced by increasing the isolation resistance (Riso1 and Riso2) of the power FET. An increase in the isolation resistance increases the duration of the inrush current event.
The discharge overcurrent limit and delay are the secondary limits that identify the damaged load or system (still running after damage) or the wrong load is connected to the battery pack. DOC conditions exist much longer and require fewer factors to consider than DSC.
The charge overcurrent limit prevents overcharging of the battery and charging the battery pack with the wrong charger. The COC delay allows unregulated charge to flow to the battery in a short period of time. Figure 5 shows the load curve of a scooter. The engine charges the battery when the current is negative. The regenerative current from the engine may be significantly greater than the charging current. The COC limit setting is close to the charger current to prevent charging the battery with the wrong charger. Most regenerative currents have a short duration. In Fig. 5, the regenerative current recorded after 250 seconds is the case when the motorcycle is going downhill. The regenerative current at about 280 seconds is the case where the motorcycle coasts to a stop. The battery pack has a charging current of 2A.
The setting of the charging current involves many factors. The main factor is the charge acceptance of the cell itself. Other factors include charging time, cell heating and battery aging.
The main reason for detecting the cell temperature is to ensure that the battery does not reach thermal runaway. The conditions that may cause thermal runaway are overcharging of the cell, short circuit to the battery pack, or internal short circuit of the cell itself. Some chemical batteries are relatively susceptible to thermal runaway.
In addition to thermal runaway detection, thermal detection is also used in practice to determine if the battery is charging or discharging safely. As shown in Figure 6, most lithium batteries provide a recommended charge/discharge temperature range. In applications such as notebook computers, it may be desirable to charge in the only allowable discharge temperature zone of Figure 6. JEITA is a lithium battery charging standard. The standard advocates reducing the charging current in a temperature zone where the cell is not very stable or is less able to accept charge. Figure 7 is an example of the JEITA charging standard. For most applications, the curve of Figure 6 is sufficient for the requirements and is easy to implement.
For stand-alone BMS ICs, it is important to understand the performance of their function blocks and power FETs in the work area. Some ICs allow charging when both the charge FET (CFET) and the discharge FET (DFET) are both on. Other ICs turn off the CFET. The CFET must never be turned off in a series power FET configuration when the cell temperature profile only allows the discharge region to operate. Running the load while the CFET is off allows current to pass through the body diode of the CFET. This increases the power dissipation of the FET, causing the FET temperature to rise. If no measures are taken to eliminate the heat generated by the FET, such as through circuit layout or the use of a heat sink, the component may be damaged. CFET shutdown when operating in a series configuration also reduces load power consumption that can affect application performance.
Most small and medium battery packs use two thermistors to monitor temperature. One of the thermistors is located in the center of the battery pack, and the temperature here is higher due to isolation from the battery cells. These cells age faster because of the higher operating temperatures. The second thermistor is located outside the battery pack and is primarily used to measure ambient temperature. Proper temperature sensing prevents the battery from thermally escaping and ensures that it is safe to charge or discharge.